technical data 331 octal d flip-flop with common clock and reset high-performance silicon-gate cmos the in74hc273a is identical in pinout to the ls/als273. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/alsttl outputs. this device consists of eight d flip-flops with common clock and reset inputs. each flip-flop is loaded with a low-to-high transition of the clock input. reset is asynchronous and active low. ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices in74hc273a ordering information in74hc273an plastic IN74HC273ADW soic t a = -55 to 125 c for all packages function table inputs output reset clock d q lx x l hhh hll h l x no change h x no change x = don?t care logic diagram pin 20=v cc pin 10 = gnd pin assignment
in74hc273a 332 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c t r , t f input rise and fall time (figure 1) v cc =2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74hc273a 333 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to -55 c 85 c 12 5 c unit v ih minimum high-level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low - level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 v v oh minimum high-level output voltage v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low-level output voltage v in = v il or v ih ? i out ? 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v il or v ih ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 a 6.0 4.0 40 160 a
in74hc273a 334 ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit f max maximum clock frequency (50% duty cycle) (figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 5.0 24 28 4.0 20 24 mhz t plh , t phl maximum propagation delay, clock to q (figures 1 and 4) 2.0 4.5 6.0 145 29 25 180 36 31 220 44 38 ns t phl maximum propagation delay , reset to q (figures 2 and 4) 2.0 4.5 6.0 145 29 25 180 36 31 220 44 38 ns t tlh , t thl maximum output transition time, any output (figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns c in maximum input capacitance - 10 10 10 pf power dissipation capacitance (per enabled output) typical @25 c,v cc =5.0 v c pd used to determine the no-load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 48 pf timing requirements (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to-55 c 85 c 125 c unit t su minimum setup time, data to clock (figure 3) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns t h minimum hold time, clock to data (figure 3) 2.0 4.5 6.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 ns t rec minimum recovery time, reset inactive to clock (figure 2) 2.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns t w minimum pulse width, clock (figure 1) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns t w minimum pulse width, reset (figure 2) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns t r, t f maximum input rise and fall times (figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
in74hc273a 335 figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms figure 4. test circuit expanded logic diagram
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